In a computer processing system, operation speeds of dynamic random access memories used as main memories have been increased, but are still low compared with operation speeds of microprocessors. It has been reported that above fact increases a wait time of the microprocessor, and impedes fast data processing, as an access time and a cycle time of the DRAM form a bottleneck in a whole system performance. In order to eliminate a difference in the operation speed between the DRAM and microprocessor, synchronous memory devices operable in synchronization with a clock signal have recently been developed, and SDRAMs have been used as main memories for fast microprocessors. In the SDRAM, introducing of external signals, i.e., address signals and control signals as well as input/output data are carried out in synchronization with a clock signal which is namely a system clock provided by the microprocessor. Since the external signals are taken into the SDRAM device in synchronization consideration, and thereby an internal operation can be started rapidly. And since input and output data are transferred therein in synchronization with the clock signal, the accessing speed of data corresponds to the clock signal, allowing fast data transmission to be accomplished.
As one of attractive functions of the SDRAM, continuous bits per data input/output terminal make an access speed of data be more enhanced, i.e., a pipelined SDRAM. A burst length, of the pipelines SDRAM, that is the number of data bits continuously transferred to one input/output terminal in a sensing cycle (or a RAS cycle) becomes an important factor determining a capacity of data read-out in one sensing cycle in the synchronous memory device. In order to enhance the accessing speeds to be more than those of single-data-rate SDRAMs, there have been proposed double-data-rate SDRAMs that are accessible in response to each transition of the clock signal, i.e., responds to not only rising edges of the clock signal but also falling edges thereof. Either in the single- or double-data-rate SDRAMs, performance of a data transmission in the SDRAM is mostly dependent upon controlling and optimizing the burst length or relevant accessing features such as a bypass architecture, in correspondence with the clock signal. It is general that the burst length is flexible corresponding to designing options and influences the operation frequency of the clock signal.
FIG. 1 shows a circuit construction for performing a data transmission in a synchronous memory device, being comprised of pad 1, input registers 2 and 3, multiplexer 4, and output driving transistor 5. Pad 1 coupled to drain of transistor 5, and registers 2 and 3 transfers external input data to the registers and output data driven by transistor 5 to an external circuit (not shown, out of the device). The registers, 2 and 3, receive input reference signals, and stores the input data to be applied to internal circuits in response to a pair of complementary clock signals CLK and CLKB (suffix B of a signal name means a counter-logic of the signal and is identical to the numeral marked with over-bar in the corresponding drawing). Multiplexer 4 applies data generated from the internal circuits to gate of transistor 5 in response to the pair of clock signals CLK and CLKB.
In a write operation (burst length=2) of the data transmission circuit of FIG. 1, as shown in FIG. 2, each address bit of external addresses ADD are taken into the device in synchronization with an rising edge of clock signal CLK (i.e., a system clock). Addresses A and B which are used in this write operation are introduced thereinto at rising edges of the first and second cycles, respectively, of clock cycle CLK. Then, input data DATA in DA0 and DA1, and DB0 and DB1 are applied to the internal circuits through the data transmission circuit from the second cycle of clock signal CLK. DA0 and DA1 correspond to address A, and DB0 and DB1 to B. Each bits of the input data is accessed at rising and falling edges of clock signal CLK, i.e., the double-data-rate mode. However, when a read cycle is started just after the write cycle, without through a dummy cycle which is to be interposed between a write cycle and a read cycle, as shown in FIG. 2, it is impossible to write the input data bits DA1, DB0, and DB1 into memory cells designated by the addresses A and B, except DA0, because of a write recovery. Therefore, though the input data bits DA1, DB0, and DB1 are successfully taken into the device, those can not be written into memory cells selected by the addresses A and B during a write recovery period.